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MC14049UB Hex Buffers
The MC14049UB hex inverter/buffer is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. This complementary MOS device finds primary use where low power dissipation and/or high noise immunity is desired. This device provides logic-level conversion using only one supply voltage, VDD. The input-signal high level (VIH) can exceed the VDD supply voltage for logic-level conversions. Two TTL/DTL Loads can be driven when the device is used as CMOS-to-TTL/DTL converters (VDD = 5.0 V, VOL v 0.4 V, IOL 3.2 mA). Note that pins 13 and 16 are not connected internally on this device; consequently connections to these terminals will not affect circuit operation.
Features
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MARKING DIAGRAMS
16 PDIP-16 P SUFFIX CASE 648 MC14049UBCP AWLYYWW 1 16 SOIC-16 D SUFFIX CASE 751B 1 16 TSSOP-16 DT SUFFIX CASE 948F 14 049U ALYW 1 16 SOEIAJ-16 F SUFFIX CASE 966 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week MC14049UB ALYW 14049U AWLYWW
* * * * * * *
High Source and Sink Currents High-to-Low Level Converter Supply Voltage Range = 3.0 V to 18 V Meets JEDEC UB Specifications VIN can exceed VDD Improved ESD Protection on All Inputs Pb-Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol VDD Vin Vout Iin Iout PD Parameter DC Supply Voltage Range Input Voltage Range (DC or Transient) Output Voltage Range (DC or Transient) Input Current (DC or Transient) per Pin Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 1) Plastic SOIC Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value -0.5 to +18.0 -0.5 to +18.0 -0.5 to VDD +0.5 10 +45 Unit V V V mA mA mW 825 740 -55 to +125 -65 to +150 260 C C C
TA Tstg TL
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Temperature Derating: All Packages: See Figure 4. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields referenced to the VSS pin, only. Extra precautions must be taken to avoid applications of any voltage higher than the maximum rated voltages to this high-impedance circuit. For proper operation, the ranges VSS v Vin v 18 V and VSS v Vout v VDD are recommended. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2004
1
December, 2004 - Rev. 6
Publication Order Number: MC14049UB/D
MC14049UB
VDD OUTA INA OUTB INB OUTC INC VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 NC OUTF INF NC OUTE INE OUTD IND 11 14 12 15 NC = PIN 13, 16 VSS = PIN 8 VDD = PIN 1 9 10 5 7 4 6 3 2 VDD
MC14049UB
NC = NO CONNECTION
VSS
Figure 1. Pin Assignment
Figure 2. Logic Diagram MC14049UB
Figure 3. Circuit Schematic
(1/6 of circuit shown)
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 - - 55_C 25_C 125_C Min - - - Max Min - - - Typ (Note 2) 0 0 0 Max Min - - - Max Unit Output Voltage Vin = VDD or 0 "0" Level VOL 0.05 0.05 0.05 - - - 0.05 0.05 0.05 - - - 0.05 0.05 0.05 - - - Vdc "1" Level VOH Vin = 0 or VDD 4.95 9.95 14.95 - - - 4.95 9.95 14.95 - - - 5.0 10 15 4.95 9.95 14.95 - - - Vdc Input Voltage (VO = 4.5 Vdc) (VO = 9.0 Vdc) (VO = 13.5 Vdc) (VO = 0.5 Vdc) (VO = 1.0 Vdc) (VO = 1.5 Vdc) "0" Level VIL Vdc 1.0 2.0 2.5 - - - - - - - - - 2.25 4.50 6.75 2.75 5.50 8.25 1.0 2.0 2.5 - - - - - - - - - 1.0 2.0 2.5 - - - - - - - - - "1" Level VIH Vdc 4.0 8.0 12.5 4.0 8.0 12.5 4.0 8.0 12.5 Output Drive Current (VOH = 2.5 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) IOH mAdc Source - 1.6 - 1.6 - 4.7 3.75 10 30 - - - - - - 1.25 - 1.3 - 3.75 3.2 8.0 24 - - - - - - 2.5 - 2.6 - 10 6.0 16 40 - 1.0 - 1.0 - 3.0 2.6 6.6 19 - - - - - Sink IOL mAdc Input Current Iin 0.1 - 0.000 01 10 0.1 20 1.0 - mAdc pF Input Capacitance (Vin = 0) Cin Quiescent Current (Per Package) IDD 5.0 10 15 5.0 10 15 1.0 2.0 4.0 0.002 0.004 0.006 1.0 2.0 4.0 30 60 120 mAdc Total Supply Current (Note 3 and 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT IT = (1.8 mA/kHz) f + IDD IT = (3.5 mA/kHz) f + IDD IT = (5.3 mA/kHz) f + IDD mAdc 2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.002.
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MC14049UB
Vout , OUTPUT VOLTAGE (Vdc)
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SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic Symbol tTLH VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min Typ (Note 6) 100 50 40 40 20 15 80 40 30 30 15 10 Max Unit ns Output Rise Time tTLH = (0.8 ns/pF) CL + 60 ns tTLH = (0.3 ns/pF) CL + 35 ns tTLH = (0.27 ns/pF) CL + 26.5 ns Output Fall Time tTHL = (0.3 ns/pF) CL + 25 ns tTHL = (0.12 ns/pF) CL + 14 ns tTHL = (0.1 ns/pF) CL + 10 ns - - - - - - - - - - - - 160 100 60 60 40 30 tTHL ns Propagation Delay Time tPLH = (0.38 ns/pF) CL + 61 ns tPLH = (0.20 ns/pF) CL + 30 ns tPLH = (0.11 ns/pF) CL + 24.5 ns Propagation Delay Time tPHL = (0.38 ns/pF) CL + 11 ns tPHL = (0.12 ns/PF) CL + 9 ns tPHL = (0.11 ns/pF) CL + 4.5 ns tPLH ns 120 65 50 60 30 20 tPHL ns 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
ORDERING INFORMATION
Device MC14049UBCP MC14049UBCPG MC14049UBD MC14049UBDG MC14049UBDR2 MC14049UBDR2G MC14049UBDT MC14049UBDTEL MC14049UBDTR2 MC14049UBF MC14049UBFEL
Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) TSSOP-16 TSSOP-16* TSSOP-16* SOEIAJ-16 SOEIAJ-16
Shipping 2,000 Units / Box 2,000 Units / Box 2,400 Units / Box 2,400 Units / Box 2,500 / Tape & Reel 2,500 / Tape & Reel 96 Units / Rail 96 Units / Rail 2,500 / Tape & Reel See Note 7 See Note 7
7. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. 18 15 VDD = 15 Vdc
10
VDD = 10 Vdc
-55C
5
VDD = 5 Vdc +125C
5
10 15 Vin, INPUT VOLTAGE (Vdc)
18
Figure 4. Typical Voltage Transfer Characteristics versus Temperature http://onsemi.com
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MC14049UB
VDD 1 IOH 8 VSS VOH VDD 1 IOL 8 VSS VOL
VDS = VOH - VDD 0 I OH , OUTPUT SOURCE CURRNT (mAdc) -10 VGS = 5.0 Vdc 160 I OL, OUTPUT SINK CURRENT (mAdc)
VDD = VOL
VGS = 15 Vdc
120
-20 VGS = 10 Vdc
80
VGS = 10 Vdc
-30
MAXIMUM CURRENT LEVEL 40 VGS = 5.0 Vdc 0 0 2.0 4.0 6.0 8.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 10
-40 -50 -10
VGS = 15 Vdc
MAXIMUM CURRENT LEVEL 0
-8.0 -6.0 -4.0 -2.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)
Figure 5. Typical Output Source Characteristics
Figure 6. Typical Output Sink Characteristics
VDD 1 1200 1100 1000 900 825 800 740 700 600 500 400 300 200 100 0 (D) SOIC (P) PDIP tPHL 175 mW (P) 120 mW (D) OUTPUT 25 50 75 100 125 150 175 90% 50% 10% tTHL tTLH PULSE GENERATOR Vin 8 VSS CL Vout
PD , MAXIMUM POWER DISSIPATION (mW) PER PACKAGE
20 ns INPUT 90% 50% 10%
20 ns VDD
VSS tPLH VOH
VOL
TA, AMBIENT TEMPERATURE (C)
Figure 7. Ambient Temperature Power Derating
Figure 8. Switching Time Test Circuit and Waveforms
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MC14049UB
PACKAGE DIMENSIONS
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE T
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
-A-
16 9
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-A-
16 9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC14049UB
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O
16X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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CCC EE CCC EE
M
SECTION N-N
-W-
MC14049UB
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC14049UB
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC14049UB/D

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